The invention relates to a method of correcting errors in convolutional code signals and to an apparatus for performing the method, and more particularly to a method and apparatus for evaluating branch metrics in the decoding of n-PSK convolution code signals, obtaining a phase error signal which includes information on the quality of the convolution code signals, with the use of the branch metrics, obtaining control signals for the resolution of phase ambiguity in the demodulation of the convolution code signals.
In convolutional code signal decoding, for example by means of a Viterbi decoder, in principle data from a PSK demodulator are made available, the number of data streams depending in a known manner on the number of phase coding statuses. For example, in QPSK modulation, it is two. In this case, two data streams for each one bit are obtained at the output of the demodulator, these data streams inherently having interference such as noise, amplitude errors, and so forth.
However, there are still other possible kinds of interference, which do not have to do with the quality of reception at the time but instead are intrinsic in the system: that is, phase ambiguity, which is associated with the carrier recovery in the demodulator. Phase errors for QPSK Modulation is expressed in the data stream in such a way that
(a) with 180.degree. errors, both bits appear in inverted form,
(b) with +90.degree. errors, one bit appears in inverted form and both appear transposed with one another,
(c) with -90.degree. errors the other bit appears in inverted form and both appear transposed with one another.
From European Patent No. 52 463 A1, it is known in principle to distinguish invalid transitions in the trellis diagram, resulting from noise or phase ambiguity, by means of a phase ambiguity detector.
For synchronization in decoders for convolution code signals, signals must be available that furnish information on phase errors that occur. To resolve phase ambiguity by means of a phase ambiguity detector in QAM or QPSK transmission of error-correcting convolution code signals, such phase error signals are also required; see European Patent No. 52 463 A1, for instance.
In the decoding of error-correcting convolutional code signals, in particular in Viterbi decoding in accordance with the trellis diagram, so-called ACS (add-compare-select) networks are necessary for evaluating the branch metrics and ascertaining the path metrics. From the Proceedings of the IEEE, Vol. 61, No. 3, March 1973, pages 268-277, in particular page 273, it is known to assemble such ACS arithmetic units from parallel-functioning comparison stages and selection stages.
From NTC 1981, Vol. 3, pages E1.7.1-E1.7.4, it is known to assemble an ACS network for a Viterbi decoder from two adders each, one comparator, one selection stage and one register, for evaluating the branch metrics and obtaining the path metric.
U.S. Pat. No. 4,757,506, the disclosure of which is incorporated herein by reference, discloses two further alternatives for ACS networks--first, an ACS network with processing in the logical operation domain (FIG. 5), that is, representation of a binary number as a position of a logical state in a line of 2.sup.n, where n is the place number of the binary number, and second, a substantially arithmetically functioning ACS network (FIG. 6).